View OP177BRC883_2024395.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

pin connections rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultraprecision operational amplifier op177 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features ultralow offset voltage: t a = +25 8 c: 10 m v max C55 8 c t a +125 8 c: 20 m v max outstanding offset voltage drift: 0.1 m v/ 8 c max excellent open-loop gain and gain linearity: 12 v/ m v typ cmrr: 130 db min psrr: 120 db min low supply current: 2.0 ma max fits industry standard precision op amp sockets (op07/op77) general description the op177 features the highest precision performance of any op amp currently available. offset voltage of the op177 is only 10 m v max at room temperature and 20 m v max over the full military temperature range of C55 c to +125 c. the ultralow v os of the op177, combines with its exceptional offset voltage drift (tcv os ) of 0.1 m v/ c max, to eliminate the need for external v os adjustment and increases system accuracy over temperature. the op177s open-loop gain of 12 v/ m v is maintained over the full 10 v output range. cmrr of 130 db min, psrr of 120 db min, and maximum supply current of 2 ma are just a few examples of the excellent performance of this operational amplifier. the op177s combination of outstanding specifications insure accurate performance in high closed-loop gain applications. this low noise bipolar input op amp is also a cost effective alte rnative to chopper-stabilized amplifiers. the op177 provides chopper-type performance without the usual problems of high noise, low frequency chopper spikes, large physical size, limited common-mode input voltage range, and bulky external storage capacitors. the op177 is offered in both the C55 c to +125 c military, and the C40 c to +85 c extended industrial temperature ranges. this product is available in 8-pin ceramic and epoxy dips, as well as the space saving 8-pin small-outline (so) and the leadless chip carrier (lcc) packages. figure 1. simplified schematic epoxy mini-dip (p suffix) 8-pin hermetic dip (z-suffix) 8-pin so (s-suffix) nc = no connect op177brc/883 lcc (rc suffix) nc = no connect
op177a op177b parameter symbol conditions min typ max min typ max units input offset voltage v os 410 1025 m v long-term input offset voltage stability d v os /time (note 1) 0.2 0.2 m v/mo input offset current i os 0.3 1.0 0.3 1.5 na input bias current i b C0.2 1.5 C0.2 2.0 na input noise voltage e n f o = 1 hz to 100 hz 2 118 150 118 150 nv rms input noise current i n f o = 1 hz to 100 hz 2 38 38pa rms input resistance differential-mode r in (note 3) 26 45 26 45 m w input resistance common-mode r incm 200 200 g w input voltage range ivr (note 4) 13 14 13 14 v common-mode rejection ratio cmrr v cm = 13 v 130 140 130 140 db power supply rejection ratio psrr v s = 3 v to 18 v 120 125 115 125 db large signal voltage gain a vo r l 3 2 k w , v o = 10 v 5 5000 12000 5000 12000 v/mv output voltage swing v o r l 3 10 k w 13.5 14.0 13.5 14.0 v r l 3 2 k w 12.5 13.0 12.5 13.0 v r l 3 1 k w 12.0 12.5 12.0 12.5 v slew rate sr r l 3 2 k w 2 0.1 0.3 0.1 0.3 v/ m s closed-loop bandwidth bw a vcl = +1 2 0.4 0.6 0.4 0.6 mhz open-loop output resistance r o 60 60 w power consumption p d v s = 15 v, no load 50 60 50 60 mw v s = 3 v, no load 3.5 4.5 3.5 4.5 mw supply current i sy v s = 15 v, no load 1.6 2.0 1.6 2.0 ma offset adjustment range rp = 20 k w 3 3mv notes 1 long-term input offset voltage stability refers to the averaged trend line of v os vs. time over extended periods after the first 30 days of operation. excluding the initial hour of operation, changes in v os during the first 30 operating days are typically less than 2.0 m v. 2 sample tested. 3 guaranteed by design. 4 guaranteed by cmrr test condition. 5 to insure high open-loop gain throughout the 10 v output range, a vo is tested at C10 v v o 0 v, 0 v v o +10 v, and C10 v v o +10 v. specifications subject to change without notice. rev. b C2C op177Cspecifications electrical characteristics (@ v s = 6 15 v, t a = +25 8 c, unless otherwise noted) electrical characteristics op177a op177b parameter symbol conditions min typ max min typ max units input offset voltage v os 10 20 25 55 m v average input offset voltage drift tcv os (note 1) 0.03 0.1 0.1 0.3 m v/ c input offset current i os 0.5 1.5 0.5 2.0 na average input offset current drift tci os (note 2) 1.5 25 1.5 25 pa/ c input bias current i b C0.2 2.4 4 C0.2 2.4 4 na average input bias current drift tci b (note 2) 8 25 8 25 pa/ c input voltage range ivr (note 3) 13 13.5 13 13.5 v common-mode rejection ratio cmrr v cm = 13 v 120 140 120 140 db power supply rejection ratio psrr v s = 3 v to 18 v 120 125 110 120 db large-signal voltage gain a vo r l 3 2 k w , v o = 10 v 4 2000 6000 2000 6000 v/mv output voltage swing v o r l 3 2 k w 12 13.0 12 13.0 v power consumption p d v s = 15 v, no load 60 75 60 75 mw supply current i sy v s = 15 v, no load 2.0 2.5 2.0 2.5 ma notes 1 tcv os is 100% tested. 2 guaranteed by endpoint limits. 3 guaranteed by cmrr test condition. 4 to insure high open-loop gain throughout the 10 v output range, a vo is tested at C10 v v o 0 v, 0 v v o +10 v, and C10 v v o +10 v. specifications subject to change without notice. (@ v s = 6 15 v, C55 c t a +125 8 c, unless otherwise noted)
op177 rev. b C3C op177e op177f op177g parameter symbol conditions min typ max min typ max min typ max units input offset voltage v os 41010252060 m v long-term input offset voltage stability d v os /time (note 1) 0.2 0.3 0.4 m v/mo input offset current i os 0.3 1.0 0.3 1.5 0.3 2.8 na input bias current i b C0.2 1.0 1.5 C0.2 1.2 2.0 C0.2 1.2 2.8 na input noise voltage e n f o = 1 hz to 100 hz 2 118 150 118 150 118 150 nv rms input noise current i n f o = 1 hz to 100 hz 2 38 38 38pa rms input resistance differential-mode r in (note 3) 26 45 26 45 18.5 45 m w input resistance common-mode r incm 200 200 200 g w input voltage range ivr (note 4) 13 14 13 14 13 14 v common-mode rejection ratio cmrr v cm = 13 v 130 140 130 140 115 140 db power supply rejection ratio psrr v s = 3 v to 18 v 120 125 115 125 110 120 db large signal r l 3 2 k w , voltage gain a vo v o = 10 v 5 5000 12000 5000 12000 2000 6000 v/mv output voltage swing v o r l 3 10 k w 13.5 14.0 13.5 14.0 13.5 14.0 v r l 3 2 k w 12.5 13.0 12.5 13.0 12.5 13.0 v r l 3 1 k w 12.0 12.5 12.0 12.5 12.0 12.5 v slew rate sr r l 3 2 k w 2 0.1 0.3 0.1 0.3 0.1 0.3 v/ m s closed-loop bandwidth bw a vcl = +1 2 0.4 0.6 0.4 0.6 0.4 0.6 mhz open-loop output resistance r o 60 60 60 w power consumption p d v s = 15 v, no load 50 60 50 60 50 60 mw v s = 3 v, no load 3.5 4.5 3.5 4.5 3.5 4.5 mw supply current i sy v s = 15 v, no load 1.6 2.0 1.6 2.0 1.6 2.0 ma offset adjustment range r p = 20 k w 3 3 3mv notes 1 long-term input offset voltage stability refers to the averaged trend line of v os vs. time over extended periods after the first 30 days of operation. excluding the ini- tial hour of operation, changes in v os during the first 30 operating days are typically less than 2.0 m v. 2 sample tested. 3 guaranteed by design. 4 guaranteed by cmrr test condition. 5 to insure high open-loop gain throughout the 10 v output range, a vo is tested at C10 v v o 0 v, 0 v v o +10 v, and C10 v v o +10 v. specifications subject to change without notice. electrical characteristics (@ v s = 6 15 v, t a = +25 8 c, unless otherwise noted)
op177Cspecifications rev. b C4C electrical characteristics op177e op177f op177g parameter symbol conditions min typ max min typ max min typ max units input offset voltage v os 10 20 15 40 20 100 m v average input offset voltage drift tcv os (note 1) 0.03 0.1 0.1 0.3 0.7 1.2 m v/ c input offset current i os 0.5 1.5 0.5 2.2 0.5 4.5 na average input offset current drift tci os (note 2) 1.5 25 1.5 40 1.5 85 pa/ c input bias current i b C0.2 2.4 4 C0.2 2.4 4 2.4 6.0 na average input bias current drift tci b (note 2) 8 25 8 40 15 60 pa/ c input voltage range ivr (note 3) 13 13.5 13 13.5 13.0 13.5 v common-mode rejection ratio cmrr v cm = 13 v 120 140 120 140 110 140 db power supply rejection ratio psrr v s = 3 v to 18 v 120 125 110 120 106 115 db large-signal voltage gain a vo r l 3 2 k w , v o = 10 v 4 2000 6000 2000 6000 1000 4000 v/mv output voltage swing v o r l 3 2 k w 12 13.0 12 13.0 12.0 13.0 v power consumption p d v s = 15 v, no load 60 75 60 75 60 75 mw supply current i sy v s = 15 v, no load 2.0 2.5 2.0 2.5 2.0 2.5 ma notes 1 op177e: tcv os is 100% tested. 2 guaranteed by endpoint limits. 3 guaranteed by cmrr test condition. 4 to insure high open-loop gain throughout the 10 v output range, a vo is tested at C10 v v o 0 v, 0 v v o +10 v, and C10 v v o +10 v. specifications subject to change without notice. figure 2. typical offset voltage test circuit figure 3. optional offset nulling circuit (@ v s = 6 15 v, C40 c t a +85 8 c, unless otherwise noted)
op177 rev. b C5C absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 v internal power dissipation 1 . . . . . . . . . . . . . . . . . . . 500 mw differential input voltage . . . . . . . . . . . . . . . . . . . . . . 30 v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 v output short-circuit duration . . . . . . . . . . . . . . . . indefinite storage temperature range z and rc packages . . . . . . . . . . . . . . . . . C65 c to +150 c s, p package . . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c operating temperature range op177a, op177b . . . . . . . . . . . . . . . . . C55 c to +125 c op177e, op177f, op177g . . . . . . . . . . C40 c to +85 c lead temperature range (soldering, 60 sec) . . . . . . +300 c dice junction temperature (t j ) . . . . . . . C65 c to +150 c package type u ja 2 u jc units 8-pin hermetic dip (z) 148 16 c/w 8-pin plastic dip (p) 103 43 c/w 20-contact lcc (rc) 98 38 c/w 8-pin so (s) 158 43 c/w notes 1 for supply voltages less than 22 v, the absolute maximum input voltage is equal to the supply voltage. 2 q ja is specified for worst case mounting conditions, i.e., q ja is specified for device in socket for cerdip, p-dip, and lcc packages; q ja is specified for device soldered to printed circuit board for so package. figure 4. burn-in circuit ordering guide temperature package package model range description option op177az C55 c to +125 c 8-pin cerdip q-8 op177bz C55 c to +125 c 8-pin cerdip q-8 op177ez C40 c to +85 c 8-pin cerdip q-8 op177fz C40 c to +85 c 8-pin cerdip q-8 op177gz C40 c to +85 c 8-pin cerdip q-8 op177fp C40 c to +85 c 8-pin plastic dip n-8 op177gp C40 c to +85 c 8-pin plastic dip n-8 op177brc/883 C55 c to +125 c 20-pin lcc e-20a op177fs C40 c to +85 c 8-pin so so-8 op177gs C40 c to +85 c 8-pin so so-8
op177typical performance characteristics figure 6. power consumption vs. power supply figure 9. open-loop gain vs. temperature figure 12. input offset current vs. temperature figure 7. warm-up v os drift (normalized) z package figure 10. open-loop gain vs. power supply voltage figure 13. closed-loop response for various gain configurations figure 5. gain linearity (input voltage vs. output voltage) figure 8. offset voltage change due to thermal shock figure 11. input bias current vs. temperature
op177 rev. b C7C figure 15. cmrr vs. frequency figure 18. input wideband noise vs. bandwidth (0.1 hz to frequency indicated) figure 16. psrr vs. frequency figure 19. maximum output swing vs. frequency figure 14. open-loop frequency response figure 17. total input noise voltage vs. frequency figure 20. maximum output voltage vs. load resistance figure 21. output short circuit current vs. time
op177 applications information gain linearity the actual open-loop gain of most monolithic op amps varies at different output voltages. this nonlinearity causes errors in high closed-loop gain circuits. it is important to know that the manufacturers a vo specifi- cation is only a part of the solution, since all automated testers use endpoint testing and, therefore, only show the average gain. for example, figure 22 shows a typical precision op amp with a respectable open-loop gain of 650 v/mv. however, the gain is not constant through the output voltage range, causing nonlinear errors. an ideal op amp would show a horizontal scope trace. figure 22. typical precision op amp figure 23. op177? output gain linearity trace figure 24. open-loop gain linearity test circuit figure 23 shows the op177s output gain linearity trace with its truly impressive average a vo of 12000 v/mv. the output trace is virtually horizontal at all points, assuring extremely high gain accuracy. pmi also performs additional testing to insure consistent high open-loop gain at various output voltages. figure 24 is a simple open-loop gain test circuit for your own evaluation. thermocouple amplifier with cold-junction compensation an example of a precision circuit is a thermocouple amplifier that must amplify very low level signals accurately without introducing linearity and offset errors to the circuit. in this circuit, an s-type thermocouple, which has a seebeck coefficient of 10.3 v/c, produces 10.3 mv of output voltage at a temperature of 1,000c. the amplifier gain is set at 973.16. thus, it will produce an output voltage of 10.024 v. extended temperature ranges to beyond 1,500c can be accomplished by reducing the amplifier gain. the circuit uses a low-cost diode to sense the temperature at the terminating junctions and in turn compensates for any ambient temperature change. the op177, with its high open-loop gain, plus low offset voltage and drift combines to yield a very precision temperature sensing circuit. cir- cuit values for other thermocouple types are shown in table i. table i. thermo- seebeck couple type coefficient r1 r2 r7 r9 k 39.2 v/c 110 w 5.76 k w 102 k w 269 k w j 50.2 v/c 100 w 4.02 k w 80.6 k w 200 k w s 10.3 v/c 100 w 20.5 k w 392 k w 1.07 m w figure 25. thermocouple amplifier with cold junction compensation precision high gain differential amplifier the high gain, gain linearity, cmrr, and low tcv os of the op177 make it possible to obtain performance not previously available in single stage, very high-gain amplifier applications. see figure 26. for best cmr, r 1 r 2 must equal r 3 r 4 . in this example, with a 10 mv differential signal, the maximum errors are as listed in table ii.
op177 figure 26. precision high gain differential amplifier table ii. high gain differential amp performance type amount common-mode voltage 0.1%/v gain linearity, worst case 0.02% tcv os 0.0003%/c tci os 0.008%/c isolating large capacitive loads the circuit in figure 27 reduces maximum slew-rate but allows driving capacitive loads of any size without instability. because the 100 w resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high open- loop gain of the op177. figure 27. isolating capacitive loads figure 28. bilateral current source figure 29. precision absolute value amplifier
op177 rev. b C10C bilateral current source the current sources shown in figure 28 will supply both positive and negative current into a grounded load. note that z o = r 5 r 4 r 2 + 1 ? ? ? ? r 5 + r 4 r 2 r 3 r 1 and that for z o to be infinite, r 5 + r 4 r 2 must = r 3 r 1 precision absolute value amplifier the high gain and low tcv os assure accurate operation with inputs from microvolts to volts. in this circuit, the signal always appears as a common-mode signal to the op amps. the op177e cmrr of 140 db assures errors of less than 1 ppm. see figure 29. precision positive peak detector in figure 30, the c h must be of polystyrene, teflon*, or polyethylene to minimize dielectric absorption and leakage. the droop rate is determined by the size of c h and the bias current of the op41. precision threshold detector/amplifier in figure 32, when v in < v th , amplifier output swings nega- tive, reverse biasing diode d 1 . v out = v th if r l = . when v in 3 v th , the loop closes, v out = v th + v in v th () 1 + r f r s ? ? ? ? c c is selected to smooth the response of the loop. *teflon is a registered trademark of the dupont company. figure 31 . precision threshold detector/amplifier figure 30. precision positive peak detector
op177 rev. b C11C outline dimensions dimensions shown in inches and (mm). 8-pin cerdip (q-8) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min 0.055 (1.4) max 1 pin 1 4 5 8 0.310 (7.87) 0.220 (5.59) 0.405 (10.29) max 0.200 (5.08) max seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 8-pin plastic dip (n-8) pin 1 0.280 (7.11) 0.240 (6.10) 4 5 8 1 seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-pin so (so-08) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 4 5 1 8 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.1968 (5.00) 0.1890 (4.80) 20-pin lcc (e-20a) top view 0.358 (9.09) 0.342 (8.69) sq 1 20 4 9 8 13 19 bottom view 14 3 18 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) bsc 0.200 (5.08) bsc 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37)
c2087C5C11/95 printed in u.s.a. C12C

▲Up To Search▲

Price & Availability of OP177BRC883

	To Download OP177BRC883 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .